By Richard F. Tinder
Asynchronous Sequential computer layout and research presents a lucid, in-depth therapy of asynchronous country computer layout and research offered in components: half I at the historical past basics with regards to asynchronous sequential good judgment circuits normally, and half II on self-timed structures, high-performance asynchronous programmable sequencers, and arbiters. half I offers an in depth assessment of the historical past basics for the layout and research of asynchronous finite nation machines (FSMs). integrated are the elemental types, use of absolutely documented nation diagrams, and the layout and features of easy reminiscence cells and Muller C-elements. basic FSMs utilizing C-elements illustrate the layout method. The detection and removal of timing defects in asynchronous FSMs are coated intimately. this can be through the array algebraic method of the layout of single-transition-time machines and use of CAD software program for that function, one-hot asynchronous FSMs, and pulse mode FSMs. half I concludes with the research tactics for asynchronous nation machines. half II is worried frequently with self-timed platforms, programmable sequencers, and arbiters. It starts off with an in depth therapy of externally asynchronous/internally clocked (or pausable) structures which are delay-insensitive and metastability-hardened. this is often through defect-free cascadable asynchronous sequencers, and defect-free one-hot asynchronous programmable sequencers--their features, layout, and purposes. half II concludes with arbiter modules of assorted forms, people with and with no metastability security, including purposes.
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Additional info for Asynchronous Sequential Machine Design and Analysis: A Comprehensive Development of the Design and Analysis of Clock-Independent State Machines and Systems ... Lectures on Digital Circuits & Systems)
4a indicates the presence of an ORG if the FSM transits from origin state 01 to destination state 10 via state 00 under branching conditions �B. In this case, the origin and destination states have the same output action relative to output Z, that is, neither state can issue an output under branching condition �B. If the FSM should transit 01 → 10 via race state 00, an ORG will occur. 7 is this ORG that is a positive 0 → 1 →0 glitch of strength equal to the path delay of an inverter. The transition 01 → 10 via race state 11 under branching condition �B, should it occur, would not produce an ORG because the output action in that state is conditional on an active input A.
For now, the cardinal rule to be followed can be stated as follows: Cardinal Rule Always design or analyze a logic circuit in mixed-logic notation and symbology. Use of positive logic or voltage-level notation must be left to the hardware implementation stage. Following this cardinal rule can help users avoid numerous errors and failure. The reader will learn that asynchronous state machine design and analysis is complex, requiring a simplified notation that maximizes the probability of success.
1 and Appendix A for details. 7 demonstrating the difference between the LPD and nested C-element model by using the wireless-connection feature. 6a. (b) Blowup view of the shaded region in (a) showing the transition from state 00 to state 11 via don’t care state 10. 4a, where use is again made of mixed-logic notation. 6a. Notice that the circuit is initialized to the 00 state by setting the clear input CL(L) = 1(L) for a short period. 6a. The transitions 00 → 11 and 11 → 00 follow paths via the state 01 or don’t care state 10 as they must.